The present invention relates to a logical device comprising a combinational circuit and a sequential circuit for holding output data of the combinational circuit, the sequential circuit comprising an input portion for receiving output data from the combinational circuit, an output portion for supplying output data of the sequential circuit to the combinational circuit, a check data input terminal for sequentially receiving test data and a check data output terminal for reading out output data of the combinational circuit. The present invention also relates to a method for testing such a logical device.
A combinational circuit can be tested by applying test data to its inputs and checking the output data that is generated at its outputs. It is more difficult to test a combinational circuit in a logical device as defined in the preamble, because the outputs of the combinational circuit also depend on a status of the sequential circuit, i.e. on a status of flip-flops contained therein.
As one example of a testing method that effectively deals with the sequential circuit, the Japanese Patent Application Laid-open No. 76037/79 discloses a logical device in which the flip-flops are chained to each other to form so-called scan paths, i.e. shift registers. The conventional device comprises a check data input terminal through which the shift registers sequentially receive a plurality of bits of check data and a check data output terminal from which the tested check data from the shift register are sequentially read out.
However, the conventional device does not enable transition testing from first check data to second check data. In the conventional device, the status of the combinational circuit may be changed during sequentially receiving a plurality of check data in the shift registers.
Furthermore, in the conventional device it is not possible to check a delay time of the output signal of the combinational circuit, in response to a transition of the check data. The delay time depends on the status of the combinational circuit. Assume, for example, that the combinational circuit is an adder and the previous output data of the adder are "1111". When the adder is incremented by adding "0001", the output data of the adder will be "0000". As another example, assume that the previous output data of the adder are "1110". When the adder is incremented by adding "0001", the output data of the adder will be "1111". The delay time in case of the previous output data "1111" may be different from the delay time in case of the previous output data "1110" because of the carry generation. In the conventional device, since it is not possible to establish a transition from first check data to second check data, the delay time in response to the other check data can not be measured.